1 p/n:pm0860 rev. 1.0, oct. 03, 2001 features ? bit organization - 4mb x 8 (byte mode) - 2mb x 16 (word mode) fast access time - random access:80/25ns(max.) page size - 8 words per page current - operating:40ma - standby:15ua(max.) supply voltage - vcc : 2.7 ~ 3.6v - vccq : 2.7 ~ 3.6v package - 64 ball mini bga (10.0mm x 13.0mm, ball pitch 1.0mm) - 56 pin tsop (14mm x 20mm) temperature - -25~85 c pin description symbol pin function a0~a21 address inputs, a0 not used in word mode d0~d15 data outputs ce0#, ce1# chip enable input ce2# oe# output enable input byte# word/byte mode selection vcc power supply pin vccq output vcc pin gnd ground pin nc no connection pin configuration mx23l3216 32m-bit mask rom preliminary 56 tsop (normal type) chip enable truth table ce2# ce1# ce0# device l l l enabled l l h disabled l h l disabled l h h disabled h l l enabled h l h enabled h h l enabled h h h disabled note: for single-chip applications, ce2#, ce1# can be strapped to gnd. nc ce1# a21 a20 a19 a18 a17 a16 vcc a15 a14 a13 a12 ce0# nc nc a11 a10 a9 a8 gnd a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nc nc oe# nc d15 d7 d14 d6 gnd d13 d5 d12 d4 vccq gnd d11 d3 d10 d2 vcc d9 d1 d8 d0 a0 byte# nc ce2# 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 mx23l3216
2 p/n:pm0860 rev. 1.0, oct. 03, 2001 mx23l3216 64 mini bga (top view, balls facing down) ce# oe# byte# d0~d7 d8~d15 power disabled x x high z high z stand-by enabled h x high z high z active enabled l l d0~d7 high z active enabled l h d0~d7 d8~d15 active mode selection order information part no. speed package grade mx23l3216ti-80 80ns 56 pin tsop industrial mx23l3216ti-10 100ns 56 pin tsop industrial mx23l3216ti-12 120ns 56 pin tsop industrial mx23l3216xi-80 80ns 64 ball mini bga industrial mx23l3216xi-10 100ns 64 ball mini bga industrial mx23l3216xi-12 120ns 64 ball mini bga industrial note: industrial grade temperature: -25 ~ 85 c commercial grade temperature: 0 ~ 70 c a1 a1 b1 a2 c1 a3 d1 a4 e1 d8 f1 byte# a2 a6 b2 gnd c2 a7 d2 a5 e2 d1 f2 d0 a3 a8 b3 a9 c3 a10 d3 a11 e3 d9 f3 d10 a4 nc b4 ce0# c4 a12 d4 nc e4 d3 f4 d11 a5 a13 b5 a14 c5 a15 d5 nc e5 d4 f5 d12 a6 vcc b6 nc c6 nc d6 nc e6 nc f6 nc a7 a18 b7 a19 c7 a20 d7 a16 e7 d15 f7 nc a8 nc b8 ce1# c8 a21 d8 a17 e8 nc f8 oe# g1 nc h1 ce2# g2 a0 h2 nc g3 d2 h3 vcc g4 vccq h4 gnd g5 d5 h5 d13 g6 d6 h6 gnd g7 d14 h7 d7 g8 nc h8 nc 10.0 mm 13.0 mm
3 p/n:pm0860 rev. 1.0, oct. 03, 2001 mx23l3216 absolute maximum ratings item symbol ratings voltage on any pin relative to vss vin -0.3v to 3.9v ambient operating temperature topr -25 c to 85 c storage temperature tstg -65 c to 125 c dc characteristics (ta = -25 c ~ 85 c, vcc = 2.7v~3.6v) item symbol min. max. conditions output high voltage voh 2.4v - ioh = -400ua output low voltage vol - 0.4v iol = 1.6ma input high voltage vih 2.2v vccq+0.5v input low voltage vil -0.5v 0.8v input leakage current ili - 10ua 0v, vcc output leakage current ilo -10 10ua 0v, vcc operating current icc - 40ma f=5mhz, ce#=vil, oe#=vih all output open standby current (cmos) istb - 15ua ce#>vcc-0.2v input capacitance cin - 10pf ta = 25 c, f = 1mhz output capacitance cout - 10pf ta = 25 c, f = 1mhz ac characteristics (ta = -25 c ~ 85 c, vcc = 2.7v~3.6v) item symbol 23L3216-80 23l3216-10 23l3216-12 min. max. min. max. min. max. read cycle time trc 80ns - 100ns - 120ns - address access time taa - 80ns - 100ns - 120ns chip enable access time tace - 80ns - 100ns - 120ns page mode access time tpa - 25ns - 25ns - 25ns output enable time toe - 25ns - 25ns - 25ns output hold after address toh 0ns - 0ns - 0ns - output high z delay thz - 20ns - 20ns - 20ns note:output high-impedance delay (thz) is measured from oe# or ce# going high, and this parameter guar- anteed by design over the full voltage and temperature operating range - not tested.
4 p/n:pm0860 rev. 1.0, oct. 03, 2001 mx23l3216 ac test conditions input pulse levels 0.4v~2.4v input rise and fall times 5ns input timing level 1.5v output timing level 1.5v output load see figure 100pf output load capacitance timing diagram page read random read tace taa toh thz add add add add ce# oe# data valid valid valid trc toe note:no output loading is present in tester load board. active loading is used and under software programming control. output loading capacitance includes load board's and all stray capacitance. dout c<100pf iol (load)=1.6ma ioh (load)=-400ua a4-a21 a0,a1,a2,a3 data note: ce#, oe# are enable. page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode. valid add valid 1'st add 2'nd add tpa taa 3'rd add valid valid
mx23l3216 m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.
|
